The present invention relates to bias voltage generators and more particularly to bias voltage generators for use in CMOS comparators.
For a better understanding of the present invention, a typical CMOS comparator 10 is shown in FIG. 1. As is typical of any comparator, there is an inverting input 22, a noninverting input 20, and an output 25. This typical prior art comparator uses P channel transistors 12 and 14 as active loads for the input pair of N channel transistors 16 and 18. The bias current for the input pair of transistors 16 and 18 and active loads is provided by the drain of N channel transistor 26. The gate of transistor 26 is biased by a bias voltage designated V.sub.BIAS. Ideally, this bias voltage is set to a voltage that enables the common mode output voltage of the comparator 10 (the output voltage that results when the positive input 20 and negative input 22 are tied together) to track the actual threshold voltage of the next stage coupled to the comparator output 25. Such a bias voltage maximizes speed and sensitivity and minimizes the input offset voltage of the comparator.
Two prior art bias generators 28 and 36 are shown in FIGS. 2 and 3. Bias generator 28 is a simple voltage divider including N channel transistors 30 and 4, both of which have the drain and gate coupled together. The bias voltage generated by bias generator 28 attempts to match the process and environmental variations experienced by transistors 16 and 26 of comparator 10 in FIG. 1. However, in actual practice, the matching is not ideal and the combination of bias generator 28 and comparator 10 in FIG. 1 results in an output voltage that is sensitive to process, environmental, and common mode voltage variations. The bias generator 36 shown in FIG. 3 has transistors 38, 30 and 34 that attempt to match transistors 12, 16 and 26 of CMOS comparator 10 in FIG. 1. The generated bias voltage at terminal 24, when coupled to CMOS comparator 10 in FIG. 1, results in an improved common mode output voltage. However, the output voltage is still sensitive to process, environmental, and common mode voltage variations.
Another prior art circuit, a comparator 46 with self generated bias voltage, is shown in FIG. 4. This comparator is identical to the prior art comparator 10 shown in FIG. 1, with the exception that the bias voltage input at the gate of transistor 26 has been coupled to the gates of transistors 12 and 14. In this way, transistor 26 is provided with an internally generated bias voltage that provides some measure of improvement in the common mode output voltage.
Bias voltage generators 28 and 36 and comparator 46 shown in FIGS. 2-4 result in a common mode output voltage that is more insensitive to common mode input voltage, process, and environmental variations than a constant bias voltage. However, the bias voltage generated by these circuits does not change in response to the input threshold voltage of the next stage driven by the comparator. What is desired is a more accurate CMOS comparator bias generator that changes in response to fluctuations in the input threshold voltage of the next stage in order that comparator speed and sensitivity are maximized and input offset voltage is minimized.